1. Field of the Invention
The present invention relates to rewritable nonvolatile memory, such as EEPROM (Electrically Erasable and Programmable Read Only Memory), and more specifically, to a technology for increasing the number of rewritable times thereof.
2. Description of Related Art
Development of EEPROM represented by flash memory is progressing in recent years. Although EEPROM can rewrite data, there is a maximum in its number of times of rewriting, and increase in the number of times of rewriting is being sought. However, with higher integration of LSI (Large Scale Integration), memory is asked for a lowered voltage, which has become hindrance of improvement in the number of times of rewriting.
In order to increase the number of times of rewriting, there is disclosed a configuration such that a sector constituting a data memory area is divided into plural memory blocks each having a size more than or equal to the data size of user adjustment data, and in the memory block, a user adjustment data area for the user adjustment data and a writing discrimination area for indicating whether the user adjustment data has been written are provided therein (refer to Patent Document 1, Japanese Patent Application Laid Open No. 2002-007221). In this configuration, a memory block where a value indicating an unwritten state stored in the writing discrimination area is searched, and new user adjustment data gets stored in the user adjustment data area of the memory block.
FIG. 22 shows a type of memory configuration. In this configuration, a read value is determined by comparing and amplifying a value of a selected memory cell 501 and a value of a reference circuit 502 with a sense amplifier SA. Therefore, it is possible to determine whether the read value is “1” or “0” by setting a cell value after erasing lower than the reference circuit 502 and setting the cell value after writing higher than the reference circuit 502. The Patent Document 1 is predicated on application to the type of the memory configuration.
FIG. 23 shows a configuration of complementary type memory. In this configuration, the sense amplifier SA compares the values of the two cells a, b that make a pair and performs determination of “1” or “0” according to which is higher. Since this configuration does not need a reference circuit, it is advantageous to voltage lowering.